The present invention is a compact register set using a pseudo-static random access memory array and a set of latches for use in a VLSI, high speed disk controller application in conjunction with a microcontroller or a microprocessor.
Registers for a high speed disk controller application, whether internal or external to the controller integrated circuit, typically are implemented in a static random access memory (SRAM) array. This is because a SRAM has some very desirable characteristics. Data can be written to or read from a SRAM with a minimal amount of set up time before the information on the address lines and the data lines can be used by the SRAM array internal control circuits. Additionally, on a read from memory, once the address lines are read into the SRAM internal control circuits and the chip select line becomes inactive, further changes to the address lines will not affect the output data. The problem with SRAMs and SRAM arrays is the physical size required for each of the memory elements which make up a memory word location. If this were not the case, SRAMs would be more widely used for main memory applications instead of the dynamic RAMS which have a much smaller memory element size, but also have slower data access times.
A simpler and smaller variation of the SRAM does exist and, because it does not have all of the same characteristics of a SRAM, is designated as a pseudo-static RAM (PSRAM). The memory element of this PSRAM uses interconnected CMOS transistors in the familiar flip-flop type of positive feedback configuration used in SRAMs, but the transistors used are physically smaller. The smaller size of the transistors does increase the desirability of such a memory, since it takes up less semiconductor chip area. Unfortunately, it also reduces the gain of those transistors, thereby reducing the overall switching performance. Partly because of the reduced performance and partly to reduce the overall size of a PSRAM memory element, the input/output circuits are simplified with respect to the input/output circuits of a SRAM array. The input/output simplification consists of using only a single transistor to interface each memory element to the column line associated with its respective bit position. In a read operation, each of the column lines is pre-charged by a CMOS switch and each memory element of the addressed word etiher keeps its output at the precharge level if that element is in the RESET state, or pulls the column line to a low level if the element is in the SET state. Each column line level is connected to an inverting buffer amplifier which ultimately provides the output. The problem with this type of PSRAM array circuit has been that, unlike the SRAM array, if the value on the address lines of the addresses bus change, the subsequently addressed location of the PSRAM array will have its memory elements drive the column lines too. Since the output of each element is wire-or'ed with the other bits of the same bit position, the resulting data output will be the same where the value stored in the locations are equal, but the pulled down level will dominate where there is a difference of the two data words. After a column line has been precharged and pulled down, there is no mechanism in the PSRAM circuit for restoring the column line to a high level except by a further precharge cycle. The susceptibility to changes on the address bus and the resulting jumbling of data that can occur has caused the PSRAM array to find limited application as a replacement for a SRAM array.
It is an object of this invention to provide a circuit arrangement which occupies less semiconductor area per memory location than equivalent SRAM registers.
It is another object of this invention to provide a circuit arrangement which holds its data output to the value accessed by the last valid address on the address bus.
It is a further object of this invention to provide a circuit arrangement which from the output characteristics thereof appears to the microcontroller or microprocessor as a SRAM array.